Sketched oxide single-electron transistor

Nature Nanotechnology, em 18/04/2011

Abstract

Devices that confine and process single electrons represent an important scaling limit of electronics^{1, 2}. Such devices have been realized in a variety of materials and exhibit remarkable electronic, optical and spintronic properties^{3, 4, 5}. Here, we use an atomic force microscope tip to reversibly ‘sketch’ single-electron transistors by controlling a metal–insulator transition at the interface of two oxides^{6, 7, 8}. In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of ~1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelectricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms.

Main

The discovery of a high-mobility quasi-two-dimensional electron gas (q-2DEG) at the interface of two insulating oxides, TiO₂-terminated SrTiO₃ and LaAlO₃ (ref. 6), has stimulated interest in the development of oxide-based electronics. The transition between insulating and conducting states in this system is an atomically sharp function of the number of LaAlO₃ unit cells⁷. At or below a thickness of three unit cells of LaAlO₃, the interface is insulating, but for four or more unit cells the interface is conducting. The conductance of films grown at a critical thickness (three-unit-cell LaAlO₃/SrTiO₃) can be locally and reversibly controlled using a conductive atomic force microscope (c-AFM) probe technique⁸. Positive voltages applied to the c-AFM tip locally switch the three-unit-cell LaAlO₃/SrTiO₃ interface to a conducting state, and negative voltages locally restore the insulating state. The writing mechanism is believed to be governed by a ‘water cycle’⁹ in which the top LaAlO₃ surface is locally charged through hydrogen passivation, resulting in high-resolution modulation doping of the LaAlO₃/SrTiO₃ interface. Using this technique, it is possible to create nanowires as small as 2 nm wide (ref. 10), islands as small as 1 nm in diameter (ref. 10), tunnel barriers¹⁰, rectifying junctions¹¹, ‘SketchFET’ transistors¹⁰ and photoconductive switches¹² with comparably small dimensions. Cryogenic operation of these devices¹³ raises the possibility that single-electron devices may also be created.

Here, we report the creation and electronic characterization of a ferroelectric sketch-based single-electron transistor (SketchSET) at the three-unit-cell LaAlO₃/SrTiO₃ interface. These devices were created using the same c-AFM lithography technique presented in ref. 8. SketchSET devices can be created in a variety of ways, one of which is illustrated in Fig. 1a,b. Two crossed nanowires are written at the LaAlO₃/SrTiO₃ interface to a conducting state. The c-AFM tip is then positioned at the intersection, and an erase pulse is applied (duration, t_b; tip voltage, V_tip = V_erase < 0), followed by a brief positive pulse (duration, t_d; V_tip = V_write > 0). This procedure creates an ultrasmall island that behaves as a quantum dot at the intersection. The quantum dot is surrounded by an insulating barrier and is separated from the four nanowires by a narrow tunnel barrier. The c-AFM tip is then positioned at the intersection, and an erase pulse is applied (duration, t_b; tip voltage, V_tip = V_erase < 0), followed by a brief positive pulse (duration, t_d; V_tip = V_write > 0). This procedure creates an ultrasmall island that behaves as a quantum dot at the intersection. The quantum dot is surrounded by an insulating barrier and is separated from the four nanowires by a narrow tunnel barrier. The centre island, produced by a 10 ms write pulse, is estimated to have a diameter d of ~1.5 nm, based on a calibration of the writing process performed on the same sample (see Supplementary Information). One can roughly estimate the number N of electrons able to reside within the quantum dot, based on typical two-dimensional carrier densities for nanoscale writing (n ≈ 5 × 10¹³ cm⁻²) at the LaAlO₃/SrTiO₃ interface: N = πd²n/4 ≈ 1 electron. This estimate agrees well with the observed behaviour, described in detail below.

a, c-AFM sketching of a single-electron transistor device. b, Energy illustration of the SketchSET device. The vertical scale has arbitrary units, but reflects the relative electron energy barrier height. Quantum-dot tunnel barriers are created by applying a negative voltage pulse of duration tb. The quantum dot is formed by applying a positive voltage pulse of duration td. c, Differential conductance Gsd from source to drain at T = 16 K. Conductance is suppressed at low biases and increases rapidly above a threshold voltage of ~0.2 V. The red curve is an exponential fit to the data. The peaks in the inset are Coulomb peaks after subtracting an exponential background. Numbers with arrows indicate electron occupation.

Electrical transport experiments were performed on six different devices, including one control structure on which no island was written. Here, we describe the results obtained for three devices (A, B and C), which were created using the parameters described in Supplementary Table S1 and Fig. S2. The experiments focus on the effect of the side gates (V_g1 and V_g2) and back gate (V_gb) on the source–drain differential conductance (G_sd) and capacitance (C_sd). Figure 1c shows the differential conductance curve for device A immediately after cooldown, with the side gates and V_gb all grounded, and the drain V_d (where current is measured) held at virtual ground. For sufficiently small source–drain voltage (V_sd), the differential conductance is strongly suppressed, and increases rapidly above a well-defined threshold. Although the structure is nominally symmetric, the threshold for positive and negative V_sd is generally different owing to hard-to-control variations at the scale of ~1 nm. Figure 1c shows two clearly resolved Coulomb peaks for V_sd < 0, and another three for V_sd > 0 before being obscured by the large conducting background. Subsequent voltage cycles resulted in fewer peaks (Fig. 2a). Structures that do not have islands at the intersection (such as SketchFET devices¹³) do not exhibit any Coulomb peaks.

a, Differential conductance Gsd measured at temperatures ranging from 16 K (bottom black curve) to 40 K (top pink curve) in 1 K steps. Curves are shifted by 0.6 nS for clarity. b, Source–drain capacitance Csd measured over the range in a. Curves are shifted by 1.6 pF for clarity. A sharp change in Csd corresponds to a single electron tunnelling event. The shadowed blue, red and yellow regions indicate electron occupations of 0, 1 and 2, respectively. Green regions indicate hysteretic regions where electron occupation in the quantum dot changes by ΔN = ±1. c, Gsd measured at T  = 30 K for forward (red) and reverse (blue) source–drain bias sweep directions. The Coulomb peaks are shifted by ferroelectric polarization in the SrTiO3. d, Coulomb peak width versus temperature. A kink is observed at TC1 = 25 K, coincident with a ferroelectric phase transition in the SrTiO3. e, Schematic band diagram showing resonant tunnelling at Vsd = 0 V in the forward sweep direction. The red arrow indicates the direction of ferroelectric polarization P. f, For the reverse sweep, the polarization is reversed (−P) and the electrochemical potential of the dot is lowered by Δφ so that the system is in the Coulomb blockade regime.

Here, we focus on transport for SketchSET devices in the low-conductance regime. Figure 2a,b shows the differential conductance G_sd and capacitance C_sd of device A as a function of temperature (16–40 K) and source–drain voltage V_sd (–0.3 V to 0.3 V), with all three side gates and the back gate grounded. The conductance exhibits distinct Coulomb peaks, which are associated with resonant tunnelling into the quantum dot (Supplementary Fig. S3). Coinciding with these conductance peaks are abrupt changes in capacitance. Generally, increases in quantum dot occupancy ΔN = 1 are associated with roughly constant capacitance jumps ΔC (see also Fig. 4). In the blue shadowed regime in Fig. 2b, the conductance is negligible and the capacitance, C_sd < ΔC, is insensitive to V_sd. For these reasons, we infer that N = 0 electrons are contained in the quantum dot in this regime.

The Coulomb peaks and associated capacitance jump locations exhibit hysteresis with respect to the source–drain voltage sweep direction. The conductance peak position, peak width and hysteresis magnitude vary significantly with temperature (Supplementary Fig. S3). With increasing temperature, the peak position first shifts to more negative V_sd, then at T_C1 = 25 K it begins to increase with temperature. The width of the peak increases approximately linearly with temperature; above T = T_C1, the slope increases by a factor of five (Fig. 2d).

The observed hysteresis in the Coulomb peak position is attributed to ferroelectric switching in the SrTiO₃ barrier. The lattice constants of LaAlO₃ and SrTiO₃ are 3.789 Å and 3.905 Å respectively (3% mismatch), and the three-unit-cell LaAlO₃ is coherently strained biaxially to match the SrTiO₃ lattice constant. The profound effect of strain on thin SrTiO₃ layers is well known^{14, 15, 16, 17}. Field-emission experiments on LaAlO₃/SrTiO₃-based SketchFET devices¹³ show evidence of a diverging dielectric permittivity associated with structural phase transitions in the near-interface SrTiO₃ region at T_C1 = 25 K and T_C2 = 65 K. The hysteretic behaviour observed as a function of local in-plane applied electric fields is highly non-monotonic with respect to temperature, and exhibits anomalies at a known structural transition T_C1. This hysteresis is qualitatively distinct from the hysteretic changes in polarization that have been reported for vertically gated LaAlO₃/SrTiO₃ heterostructures¹⁸. Hysteresis in both conduction and capacitance as a function of the back-gate bias is observed for device A (Supplementary Fig. S8); however, as noted in ref. 18, it is difficult to distinguish ferroelectric hysteresis from trap charging or other polarization effects in this geometry.

Ferroelectric polarization has a profound influence on the resonant tunnelling characteristics of the SketchSET, and is capable of switching the conductance of the source–drain channel between ‘on’ and ‘off’ states (Fig. 2c). At T = 30 K, when V_sd is swept in the forward direction, resonant tunnelling is observed at V_sd = 0, with G_sd = 0.3 nS. After sweeping V_sd to 0.3 V and returning to V_sd = 0, the conductance has vanished.

The effect of ferroelectric polarization on the SketchSET characteristics can be understood qualitatively by expanding the constant-interaction (CI) picture², in which there are well-defined energy levels in the quantum dot, to include the effect of ferroelectric polarization. Single-electron tunnelling occurs when an allowed energy state within the quantum dot becomes resonant with the electrochemical potential of either the source lead (μ_s) or drain lead (μ_d). Such a resonant condition is indicated in Fig. 2e. Ferroelectric tunnel barriers can shift the chemical potential within the quantum dot (by an amount Δφ) so that resonance only occurs for one polarization direction (Fig. 2f). The SketchSET can be regarded as a local sensitive detector of polarization in the SrTiO₃; however, it is only sensitive when the SketchSET undergoes resonant tunnelling.

Within the CI framework, the Coulomb peak spacing ΔV_sd can be used to estimate the addition energy E_a by ΔV_sd = E_a/eα, where the lever arm α = C_s/C_QD is the ratio between the source-to-quantum dot capacitance C_s and total quantum dot capacitance C_QD. The width of the Coulomb peak is expected to broaden linearly with temperature¹⁹: dV_sd/dT = 3.5k_B/eα, where k_B is the Boltzmann constant. From Fig. 2d, we can estimate α ≈ 0.15 for T < T_C1 and α ≈ 0.03 for T > T_C1, respectively. The addition energy below 25 K cannot be estimated, because N = 2 states are not observed. As the Coulomb peak shifts to positive values of V_sd, a second electron state emerges at T > 31 K with spacing ΔV_sd ≈ 0.3 V (Fig. 2b), which allows for an addition energy to be estimated as E_a = 9 meV and thus C_QD ≥ 18 aF. An upper limit of C_QD ≤ 40 aF can be inferred from the thermal broadening effect, which occurs at T ≈ 45 K. The energy shift caused by the ferroelectric remnant polarization can be estimated in a similar manner: ΔE_FE ≈ 2–6 meV.

There are two principal mechanisms by which the ferroelectric polarization can produce an energy shift (Supplementary Fig. S7). If the polarization is spatially uniform, then it can only couple to the dipole moment of the quantum dot. If the polarization is spatially non-uniform, then it can couple directly to the charge. The first scenario is outlined in Fig. 2e,f, but broken symmetries could lead to a situation in which the polarization breaks into non-symmetric domains. Such a case would also produce a direct ferroelectric coupling to the charge in the quantum dot.

Resonant tunnelling through the quantum dot can be modified through the application of either side gates or a back gate. The strength of the side-gate coupling can be adjusted by varying the barrier width (controlled by the duration of the erase pulse t_b) or by writing side gates a fixed distance from the quantum dot. Two examples are shown for side gates created close to the island (device B) and separated by a 50 nm gap (device A). For device A (Supplementary Fig. S4), a clearly defined resonance is shifted by ΔV_sd = 40 mV as the side gate V_g is changed from −0.2 V to +0.2 V, with no evidence of gate leakage. The low coupling factor, ΔV_s/ΔV_g = 0.1 in this case, reflects the geometric separation of the side gate. For device B, the gates are separated by approximately the same distance as the source and drain leads; hence, significant gate leakage is observed. Sharp resonances are only observed when V_g1 and V_sd have opposite signs (Fig. 3). This ‘differential mode’ is more effective in aligning the lowest quantum dot chemical potential level than the ‘common mode’ configurations (Supplementary Fig. S5).

a, Differential conductance Gsd for various side-gate voltages Vg1 = −2.5 V, −1.0 V, 0 V, 1.0 V and 2.5 V. The other side gate is grounded: Vg2 = 0 V. b, Two-dimensional plot of Gsd versus Vg1 and Vsd. A single Coulomb oscillation is observed only when Vg1 and Vsd have opposite signs. The red arrows in a and b mark resonant tunnelling.

SketchSET structures respond to modest (|V_bg| < 1 V) voltages applied to the bottom of the SrTiO₃ substrate. The sensitivity of the SketchSET to back gating, as measured by changes in the effective carrier density within the quantum dot, is more than two orders of magnitude larger than what has been reported for back-gate control of the metal–insulator at room temperature⁷ and superconductivity at low temperature²⁰. The principal reason for the relatively high sensitivity is that the high curvature of the metallic nanostructures focuses the electric flux lines, thereby greatly increasing the electric field effect at the device.

Figure 4 shows the differential conductance and capacitance as a function of back-gate bias V_bg and source–drain bias V_sd for device C. For the lowest value V_bg = −0.4 V, a single resonant peak is observed as V_sd is swept from 0 V in either the positive or negative directions. The resonant peaks mark a transition from N = 0 electrons in the quantum dot to N = 1 electrons. The increase in N is associated with a discrete jump in the measured capacitance (Fig. 4c,d), increasing from C₀ ≈ 2.5 pF for V_sd = 0 by an amount ΔC₋ = 3.5 pF (ΔC₊ = 2.5 pF) for scans with increasing |V_sd|. Although the structure is nominally symmetric with respect to source and drain, there are clear asymmetries, which result in different thresholds for positive and negative V_sd. As V_bg is increased, the resonances shift towards V_sd = 0 V (Fig. 4d), and a second resonant peak is observed on the V_sd < 0 side. The higher stability of the N = 2 state, as measured by the strong suppression of the conductance near V_sd = −0.18 V, and the greater width of the N = 2 plateau in the capacitance, is believed to be a manifestation of the well-known ‘shell filling effect’ that has been observed in two-dimensional quantum-dot systems^{21, 22} and III–V self-assembled quantum dots²³. Higher N values are not observed because the structure becomes highly conducting outside the range shown, but a similar non-uniform spacing is apparent in Fig. 4c.

a, Differential conductance (Gsd) curves at back-gate voltages Vbg from −0.4 V to 0 V in 0.02 V steps. Curves are offset by 0.2 nS for clarity. The second electron emerges at Vbg = −0.1 V. b, Intensity plot of Gsd. c, Capacitance curves at the same gating conditions as in a. Curves are offset by 0.3 pF for clarity. The discrete jumps coincide with changes in electron occupancy in the quantum dot. d, Intensity plot of Csd. Numbers in red in c and d indicate electron occupation N in the quantum dot.

A remarkable feature of the SketchSET is the high sensitivity of the capacitance to changes in electron occupation in the quantum dot. The change in capacitance (~pF) observed during a single-electron charging event at the quantum dot is approximately three orders of magnitude too large to be accounted for solely by electrostatic effects. It is well known that SrTiO₃ is a high-permittivity incipient ferroelectric with a dielectric constant that can exceed ε ≈ 1 × 10⁴ at low temperatures, which is easily perturbed by structural deformation, strain and electric fields²⁴. The presence of a single bound electron at the LaAlO₃/SrTiO₃ interface is predicted to produce a large distortion of the SrTiO₃ octahedra that extends far beyond the location of the charge⁸. This structural distortion increases the polarizability of the nearby SrTiO₃, thus increasing the parasitic capacitance C_p between source and drain (Supplementary Fig. S6). The inferred C_QD is roughly four orders of magnitude smaller than the measured capacitance C_p.

The unique properties of this ferroelectric SketchSET provide new opportunities for combining the ultrahigh electrostatic sensitivity of SET devices with ferroelectric-derived sensitivity at the nanoscale. Because all ferroelectric materials are also piezoelectric, a natural coupling between charge and nanomechanical motion is expected for the SketchSET. Furthermore, a variety of phenomena associated with the spin degree of freedom for single-electron devices^{25, 26} is expected to hold for these devices. By integrating oxide heterostructures with silicon²⁷, it may be possible to integrate ferroelectric SketchSET scanning probes that are capable of measuring charge and displacement simultaneously at the nanoscale²⁸. The existence of a ferroelectrically programmable SET constitutes a new type of nanoscale memory architecture that could be useful for low-power, ultrahigh-density storage, if the charging energy and ferroelectric polarization could be made to persist to room temperature^{14, 15, 27}. The method for creating a single SketchSET is readily replicated as one- or two-dimensional arrays, which may find use in quantum dot-based quantum computation²⁹ or as a versatile solid-state ‘Hubbard toolbox’³⁰ capable of exploring new artificial quantum states of matter.

Method

The three-unit-cell LaAlO₃/SrTiO₃ samples for devices A, B and C were grown at 780 °C with an oxygen background pressure of 7.5 × 10⁻⁵ mbar using pulsed laser deposition. The samples were then patterned with six gold electrodes contacting the interface by ion milling 25 nm and backfilling with 2 nm titanium and 23 nm gold. AFM lithography was carried out using a commercial atomic force microscope (Asylum Research MFP-3D) under conditions of controlled relative humidity (40%). The tip position was controlled by a custom-made Labview program that converts graphic information to voltage commands, which are sent to the AFM scanner. Before writing the SketchSET device, the sample surface was cleaned by slowly scanning the AFM tip with an applied voltage of −10 V to remove residue charges at the interface. During writing, conductance between the electrodes of interests was monitored simultaneously. Transport measurements were performed using a dual-phase lock-in amplifier at 25.5 Hz. The lock-in phase was adjusted so that the x channel reflected the conductance and the y channel reflected the capacitance.

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Acknowledgements

This work was supported by US National Science Foundation (DMR-0704022 and DMR-0906443), US Defense Advanced Research Projects Agency (W911NF-09-10258), US Army Research Office (W911NF-08-1-0317), The Fine Foundation, US Air Force Office of Scientific Research (FA9550-10-1-0524), a David and Lucile Packard Fellowship and the Fundação de Amparo à Pesquisa do Estado de São Paulo – FAPESP (contact project 05/04643-7).

Author Information

Affiliations
Department of Physics and Astronomy, University of Pittsburgh, Pittsburgh, Pennsylvania 15260, USA
Guanglei Cheng,Feng Bi,Cheng Cen,Daniela F. Bogorin &Jeremy Levy

Laboratório Nacional de Luz Síncrotron, Caixa Postal 6192, 13083-970 Campinas SP, Brazil
Pablo F. Siles
Instituto de Física ‘Gleb Wataghin’, Universidade Estadual de Campinas-UNICAMP, Campinas SP, Brazil
Pablo F. Siles
Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706, USA
Chung Wung Bark,Chad M. Folkman,Jae-Wan Park &Chang-Beom Eom
Hewlett Packard Laboratories, 1501 Page Mill Road, Palo Alto, California 94304, USA
Gilberto Medeiros-Ribeiro
Contributions
G.C. carried out the major experiments. P.F.S. and C.C. carried out preliminary experiments. F.B., G.C. and D.F.B. contributed to device fabrication. C.W.B., C.M.F., J.W.P. and C.B.E. contributed to sample growth. J.L., G.C., C.C. and G.M.R. discussed and analysed the results. All authors contributed to writing of the manuscript.

Competing financial interests
The authors declare no competing financial interests.

Corresponding author
Correspondence to: Jeremy Levy

Supplementary information

Supplementary information